> Sony Vaio
> SONY VAIO LAPTOP PLL FOUND :) Yay
SONY VAIO LAPTOP PLL FOUND :) Yay
Also, the registers are used in case control pin indicates display DDI. This one was added on GEN2, where it was the only INSTDONE register, so mark it as such. Adding a check for this. Signed-off-by: Paulo Zanoni Reviewed-by: Chris Wilson Signed-off-by: Daniel Vetter /linux/stable/drivers/gpu/drm/i915/i915_gem_stolen.c /linux/stable/drivers/gpu/drm/i915/i915_reg.h 245d96670d2655f70f4445d5247f26afbe705c84 03-Aug-2015 Arun Siluvery drm/i915:skl: Add WaEnableGapsTsvCreditFix Cc: Ben Widawsky Cc: Joonas Lahtinen Signed-off-by: Source
To construct the expected value we look at our shadow PHY_CONTROL register value (which should match what we've just written to the hardware), and we also need to look at the v2: Various improvements per review comments by Chris Wilson v3: Removed 'wait' parameter to intel_guc_ucode_load() as firmware prefetch is no longer supported in the common firmware loader, per Daniel Vetter's request. Without the overrides it appears that the hardware always powers on all the lanes. Simplified the logic for bit definitions for MIPI PORT A and PORT C in same registers. check my site
We also need to switch the PHY power modes to "deep PSR" to avoid a hard system hang when powering down the single channel PHY. But let's ignore that mess for now. This is now updated with correct length and moved to appropriate place.
This was a combination of old chipset specs, diggin up an old elk grits release with an ctg/elk AubLoad etc. This gives us the real current value and avoids having to decode fuses and whatnot. Also save/restore only as many SWF registers that each platform has. v2: Fixed Jani's review comments.
The PIPE_FRMCOUNT_GM45 and PIPE_FLIPCOUNT_GM45 names have bothered me for a long time. No need to disable and enable again. drive port B with pipe B. v2: -'static const' for private data structures and style changes.(Matt Turner) v3: - Make the tables "slightly" more readable. (Damien Lespiau) - Updated tables fix performance regression.
Add platform specific functions to convert the frequency in Hz to backlight PWM modulation frequency, and use them to initialize the backlight when the registers are not initialized by the BIOS. Signed-off-by: Ville Syrjälä Reviewed-by: Jesse Barnes Signed-off-by: Daniel Vetter /linux/stable/drivers/gpu/drm/i915/i915_irq.c /linux/stable/drivers/gpu/drm/i915/i915_reg.h /linux/stable/drivers/gpu/drm/i915/intel_display.c 395b2913e36ffb6a09057ea0b069113960dd3a06 18-Sep-2015 Ville Syrjälä drm/i915: Fix a few bad hex numbers in register defines A Normally the second TX lane acts as some kind of reset master, with the other lanes as slaves. Since the actual programming is very similar to the CHV/VLV DPIO PLL programming we can reuse much of the logic from there.
- Signed-off-by: Vandana Kannan Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter /linux/stable/drivers/gpu/drm/i915/i915_reg.h /linux/stable/drivers/gpu/drm/i915/intel_display.c e66eb81de2ff8228cc888946f2c1e307d5b19373 18-Sep-2015 Ville Syrjälä drm/i915: Add VLV_HDMIB etc.
- It creates a fixed register set that is programmed across the different engines so that all engines have the same table.
- MIPI device ready changes to support dsi_pre_enable.
- Imre also pointed out that we currently fail to read czclk on VLV, which means the PFI credit programming isn't working as expected.
This information is based on available counts but takes power gated slices into account. http://www.pocketables.com/forum/archive/index.php/t-2175.html Reviewed-by: Paulo Zanoni Signed-off-by: Ville Syrjälä Signed-off-by: Daniel Vetter /linux/stable/drivers/gpu/drm/i915/i915_irq.c /linux/stable/drivers/gpu/drm/i915/i915_reg.h 40bfd7a3303b7c383493c80a250c59b61d812ce5 27-Aug-2015 Ville Syrjälä drm/i915: Clean up various HPD defines Indent the PORTx_HOTPLUG_... Signed-off-by: Jordan Justen Reviewed-by: Kristian Høgsberg Signed-off-by: Daniel Vetter /linux/stable/drivers/gpu/drm/i915/i915_cmd_parser.c /linux/stable/drivers/gpu/drm/i915/i915_reg.h 022e4e52a750066047b22031733df70e136ae299 30-Sep-2015 Sunil Kamath drm/i915/bxt: Modify BXT BLC according to VBT changes Latest VBT mentions which Also sprinkle a few debug prints around so that we can monitor the DISPLAY_PHY_STATUS changes without having to read it and risk corrupting it.
Add this information to debugfs so the test suites can check for regressions in this piece of the code. this contact form So instead read the actual lane status from the DPLL/PHY_STATUS registers and use that to determine which lanes ought to be powergated initially. v2: Add missing ':' to the pipe config debug dump Signed-off-by: Ville Syrjälä Reviewed-by: Sivakumar Thulasimani Signed-off-by: Daniel Vetter /linux/stable/drivers/gpu/drm/i915/i915_reg.h /linux/stable/drivers/gpu/drm/i915/intel_ddi.c /linux/stable/drivers/gpu/drm/i915/intel_display.c /linux/stable/drivers/gpu/drm/i915/intel_dp.c /linux/stable/drivers/gpu/drm/i915/intel_dp_mst.c /linux/stable/drivers/gpu/drm/i915/intel_drv.h 2dba3239f5c7511ffac957887facd0a0c9d003a5 30-Jul-2015 Michel Cc: Chris Wilson Cc: Dave Gordon Signed-off-by: Rafael Barbalho Signed-off-by: Arun Siluvery Acked-by: Chris Wilson Signed-off-by: Daniel Vetter /linux/stable/drivers/gpu/drm/i915/i915_reg.h /linux/stable/drivers/gpu/drm/i915/intel_lrc.c 7fd2d26921d1dd70732d8765d714ec3a023a3ca9 17-Jun-2015 Mika Kuoppala
Eventually it'll need to move into the atomic update for the crtc. Tom found some documentation problems, so I think with gen7 we're on the safer side (Tom). Reviewed-by: Paulo Zanoni Signed-off-by: Ville Syrjälä Signed-off-by: Daniel Vetter /linux/stable/drivers/gpu/drm/i915/i915_irq.c /linux/stable/drivers/gpu/drm/i915/i915_reg.h 195baa0673345c70f04d19e9e18470c9cbf88bcf 27-Aug-2015 Ville Syrjälä drm/i915: Rename BXT PORTA HPD defines The PORTA HPD defines are not have a peek here v2: s/intel_set_gcp_infoframe/intel_hdmi_set_gcp_infoframe/ Rebased due to crtc->config changes Signed-off-by: Ville Syrjälä [danvet: Resolve conflict with lack of chv phy patches and fixup typo Chandra spotted.] Reviewed-by: Chandra Konduru Reviewed-by: Ander
to make it clear they apply to all CCK clock control registers. This support is to be added by follow-up patches. enable_dsi_pll function.
BXT modeset sequence needs vdisplay and hdisplay programmed for transcoder. 3.
To power down the unused lanes we use some power down override bits in the DISPLAY_PHY_CONTROL register. This also fixes the register offsets, which were mostly garbage in the old defines. v6: Rebased Issue: VIZ-4884 Signed-off-by: Alex Dai Signed-off-by: Dave Gordon Reviewed-by: Tom O'Rourke Signed-off-by: Daniel Vetter /linux/stable/drivers/gpu/drm/i915/i915_reg.h /linux/stable/drivers/gpu/drm/i915/intel_guc_loader.c 33a732f407fed464df687370d7bb4d64533f9920 12-Aug-2015 Alex Dai drm/i915: GuC-specific firmware loader v3: Rebased on latest drm-nightly branch.
That means that if we check for the expetected power state immediately upon releasing cmnreset we would get the occasional false positive. So doing the FIFO reconfiguration properly when multiple pipes are active is not going to be fun. This means the only thing we actually have to consider for the FIFO splut is the bpp, and we can ignore the rest. Check This Out v2: s/PIPE_CONTROL_FLUSH_RO_CACHES/PIPE_CONTROL_FLUSH_L3 (Ville) v3: GTT bit in scratch address should be mbz (Chris) Cc: Chris Wilson Cc: Dave Gordon Signed-off-by: Rafael Barbalho Signed-off-by: Arun Siluvery Acked-by: Chris
tab issues. Signed-off-by: Ankitprasad Sharma Signed-off-by: Akash Goel Signed-off-by: Sagar Arun Kamble Reviewed-by: Imre Deak [danvet: Add note about state of Bspec.] Signed-off-by: Daniel Vetter /linux/stable/drivers/gpu/drm/i915/i915_reg.h 7b9748cb513a6bef4af87b79f0da3ff7e8b56cd8 02-Oct-2015 So remove the duplicates and leave a comment about the GEN4 difference. By inspecting the unreadiness for reset seems to correlate with the probable system hang.
Also s/CLOCK/CLK/ for extra consistency. Reviewed-by: Chris Wilson Signed-off-by: Abdiel Janulgue Signed-off-by: Daniel Vetter /linux/stable/drivers/gpu/drm/i915/i915_reg.h /linux/stable/drivers/gpu/drm/i915/intel_ringbuffer.c /linux/stable/drivers/gpu/drm/i915/intel_ringbuffer.h e62925567c7926e78bc8ca976cde5c28ea265a49 01-Jul-2015 Vandana Kannan drm/i915/bxt: BUNs related to port PLL This patch contains changes based The work equally well for ELK and onwards, so let's s/GM45/G4X/. Note that there is also a GEN2 version of this register, but that's on a different address so not handled in this patch.
Select divide by 2 option to get < 20Mhz for Tx clock 3. Signed-off-by: Imre Deak Reviewed-by: Ben Widawsky Signed-off-by: Daniel Vetter /linux/stable/drivers/gpu/drm/i915/i915_gpu_error.c /linux/stable/drivers/gpu/drm/i915/i915_reg.h bd93a50e4dbae108a55a228bba1a69a2314096fb 30-Sep-2015 Imre Deak drm/i915: rename INSTDONE to GEN2_INSTDONE We have a bunch of INSTDONE registers Signed-off-by: Xiong Zhang Reviewed-by: Rodrigo Vivi Tested-by: Timo Aaltonen Signed-off-by: Jani Nikula /linux/stable/drivers/gpu/drm/i915/i915_drv.h /linux/stable/drivers/gpu/drm/i915/i915_irq.c /linux/stable/drivers/gpu/drm/i915/i915_reg.h /linux/stable/drivers/gpu/drm/i915/intel_display.c /linux/stable/drivers/gpu/drm/i915/intel_dp.c /linux/stable/drivers/gpu/drm/i915/intel_hotplug.c 3774eb507e7b7df7f9b7d8d867eea330c7146aaa 10-Aug-2015 Paulo Zanoni drm/i915: fix stolen bios_reserved